1. Technical Field of the Invention
The present invention relates to a chopper type comparator in a CMOS structure that is used for series type A/D converters, two-step parallel type AID converters and the like. More particularly, the present invention relates to a chopper type comparator that can reduce feed through noises of analogue switches.
2. Conventional Technology
In recent years, greater integration and greater speed in memories and microprocessor LSIs are actively pursued due to the advances made in the miniaturization technology in CMOS processes. If an analog circuit can be realized by a process compatible with that employed for these logical LSIs, digital circuits and analogue circuits can be disposed in the same chip, and higher reliability, such that reduction in size and lower cost can be realized. Therefore, realization of analogue circuits by CMOS processes is indispensable not only for A/D converters and D/A converters, but also for microprocessors on analog/digital chips, communications, and digital OA equipment.
As a comparator used in A/D converters, a chopper type DC amplifier using bipolar or FET transistors have been placed in practical use in a field where a high level of accuracy is required. In particular, MOS transistors are most suitable for chopper switches because their leak current is small and they do not generate offset voltage.
Currently, a variety of chopper type comparators with CMOS structure are studied.
FIG. 12 shows one example of a chopper type comparator with CMOS structure.
The chopper type comparator with CMOS structure shown in FIG. 12 was studied in xe2x80x9cAnalysis and Evaluation of CMOS Chopper Type Comparatorsxe2x80x9d in Vol. J67-C, No. 5 (1984) of the Journal of the Institute of Electronics and Communication Engineers.
The chopper type comparator includes an input switching circuit 101 for switching between an input voltage VIN and a reference voltage VRF, a capacitor C1 that connects to the input switching circuit 101, an amplification circuit 111 formed from amplifiers (CMOS inverters) 112 in several stages, and a compensation circuit 121.
The input switching circuit 101 is provided with a switch CT1 for turning on and off the input voltage VIN, and a switch CT2 for turning on and off the reference voltage VRF. Each of the switches CT1 and CT2 is a semiconductor element such as a MOS field effect transistor. Gate terminals are shown in the figure at upper section and lower section of the respective switches CT1 and CT2. Control driver circuits 102 and 103 are connected to the gate terminals, respectively, in which control signals CKs, and CKc are inputted, respectively. The switches CT1 and CT2 are controlled to turn on and off by the control signals CKs and CKc, respectively.
The amplification circuit 111 comprises a CMOS inverter 112. A switch CT3 that is formed from a semiconductor element such as a MOS field effect transistor is disposed in a manner to couple an input side and an output side of the CMOS inverter 112. The CMOS inverter 112 connects to a control driver circuit 113, which provides an input of a control signal CKb. The switch CT3 is controlled to turn on and off by the control signal CKb.
It is noted that the compensation circuit 121 is provided to lower an offset voltage that may be caused by the field through between the gate and the drain of the switch CT3. If the switch CT3 is composed of a CMOS switch, self-compensation of charges by the PMOS and NMOS can be expected, and therefore the compensation circuit 121 is not necessary.
Next, a method for comparison and judgment by the chopper type comparator will be described.
FIG. 13 shows a chart to describe a method for comparison and judgment by the chopper type comparator.
Referring to FIG. 13, first, the switches CT1 and CT3 are turned on (Step 101). Then, a voltage on an input side of the capacitor C1 becomes an input voltage VIN, and a voltage on an output side thereof becomes a voltage VB, such that the capacitor C1 is charged with their difference voltage (VINxe2x88x92VB). Here, the voltage VB is a logical threshold voltage of the CMOS inverter 112, and its period is called a sampling period (TS).
Next, the switch CT3 is turned off (Step 102), and the switch CT1 is turned off (Step 103) in succession.
In this instance, the switch CT2 is turned on (Step 104), and the input voltage VIN and the reference voltage VRF are compared, whose period is called a comparison period (TC).
FIG. 14 shows a timing chart indicating the above described comparison and judgment.
FIG. 14 shows a timing chart of a control signal CLK that controls the comparator shown in FIG. 12, and the control signals CKs, CKb, CKc that are inputted in the respective switches. Referring to FIG. 14, when the control signal CLK becomes LOW (TPWL), the switch CT2 is turned off 6 ns thereafter, and switches CT1 and CT3 are turned on 48 ns thereafter. As the switch CT1 is turned on, a sampling is conducted for a period TS.
When the control signal CLK becomes HIGH (THIGH), the switch CT3 is turned off 18 ns thereafter, and the switch CT1 is turned off 36 ns thereafter. As the switch CT1 is turned off, the sampling ends.
34 ns after the end of the sampling, the switch CT2 is turned on, and a comparison is conducted for the period TC.
In the chopper type comparator described above, charge noise Q is generated when the switch CT1 is turned off. The charge noise Q is called a field through noise. When the charge noised Q is generated, a voltage change of dV1=dQ1/C1 occurs, such that the CMOS inverter 112 responds thereto, and starts providing an output.
Also, as shown in FIG. 12, two inverters are used in each of the control driver circuits 102 and 103. A control signal is inputted in one of the gate terminals of each of the switches CT1 and CT2 through one inverter, and a control signal is inputted in the other of the gate terminals of each of the switches CT1 and CT2 through two inverters. As a result, a delay for one inverter stage is generated between the control signals that drive the Pch and Nch transistors in the switches CT1 and CT2, such that the Pch and Nch transistors cannot be simultaneously turned on and off, and the above-described field through noise is increased.
Also, when the capacity of the capacitor C1 is increased to suppress the value dV1 to a smaller value, a response to the value dV1 may not be completely returned within the comparison period, even when the switches CT1 and CT2 are switched at a high speed to operate the comparator at high speed. In order to return this lengthy response of the CMOS inverter and amplify the (VINxe2x88x92VB) voltage, the response speed of the CMOS inverter must be increased, which leads to an increase in its power consumption. Furthermore, the use of a chopper type comparator with a larger capacitor C1 in an A/D converter causes to lower the input band of the A/D converter, which causes to impede its high-speed operation.
The present invention has been made in view of the problems discussed above, and its object is to provide a chopper type comparator with an improved driver structure for controlling switches, which can reduce field through noise of analogue switches and which is highly effective.
To solve the problems described above, a chopper type comparator in accordance with the present invention comprises: a first switch device composed of a PMOS transistor and an NMOS transistor for switching voltage to be compared; a second switch device composed of a PMOS transistor and an NMOS transistor for switching reference voltage; a capacitor connected to an output side of both of the switch devices for storing a charge according to the voltage; an amplification inverter that is connected to an output side of the capacitor and amplifies a capacitor output signal of the capacitor; a first control driver circuit that outputs a clock signal for controlling both of the switch devices; and a second control driver circuit that outputs a clock signal for controlling both of the amplification inverter, and the chopper type comparator is characterized in that the first control driver circuit is provided with two output devices, one of the output sides of the first control driver circuit connects to a gate terminal of the PMOS transistor of the first switch device and a gate terminal of the NMOS transistor of the second switch device, or to a gate terminal of the NMOS transistor of the first switch device and a gate terminal of the PMOS transistor of the second switch device, and another of the output sides of the first control driver circuit connects to a gate terminal of the NMOS transistor of the first switch device and a gate terminal of the PMOS transistor of the second switch device, or to a gate terminal of the PMOS transistor of the first switch device and a gate terminal of the NMOS transistor of the second switch device, wherein an intersection of rising and falling of drive output control signals of the first control driver circuit and/or the second control driver circuit defines a center of an amplitude of a drive signal.
With the chopper type comparator of the example described above, the switch CT1 and the switch CT2 can be substantially simultaneously switched, such that the field through can be cancelled by the offset effect of NMOS and PMOS channel forming carriers, and the voltage change dV1 itself can be reduced.
Also, since the capacity of the capacitor C1 does not need to be increased to suppress the voltage change dV1 that may be caused by charge noises, a higher operation speed is attained, and a smaller chip area is achieved.
Also, a lengthy response of the inverter due to the voltage change dV1 is not outputted, and a comparison can be reliably conducted within a comparison period.
In the chopper type comparator described above, in the first control driver circuit and/or the second control driver circuit, a drive input control signal that is inputted in the driver circuits is branched to two output circuits, wherein one of the output circuits is provided with a plurality of first control inverters, and another of the output circuits is provided with a plurality of second control inverters in half the number of the first control inverters, wherein an L-size (transistor length) of transistors that form the second control inverter may preferably be two times an L-size of transistors that form the first control inverter.
When the number of inverters disposed is different, the L-size of the transistors may be changed, and the switches can be switched substantially simultaneously without a delay. By this, the field through at the time of switching can be cancelled, and a voltage change due to charge noises can be controlled, such that an elongation of the amplifier response can be suppressed.
In the chopper type comparator described above, in the first control driver circuit and/or the second control driver circuit, a drive input control signal that is inputted in the driver circuits is branched to two output circuits, wherein one of the output circuits connects to a first D flip-flop and an EXOR circuit through a plurality of control inverters, and another of the output circuits connects to a second D flip-flop and an EXOR circuit, wherein output sides of the EXOR circuits connect to both of the flip-flops, and both of the flip-flops output signals to be inputted to the flip-flops upon receiving control signals from the EXOR circuits.
By the control driver circuit described above, control signals at different levels are outputted in synchronism with one another, such that the switches can be switched substantially simultaneously without a delay. By this, the field through at the time of switching can be cancelled, and a voltage change due to charge noises can be controlled, such that an elongation of the amplifier response can be suppressed.
In the chopper type comparator described above, in the first control driver circuit and/or the second control driver circuit, a drive input control signal that is inputted in the driver circuits is branched to two output circuits, wherein one of the output circuits is provided with a first control inverter including a plurality of NAND circuits, and another of the output circuits is provided with a second control inverter including NAND circuits in half the number of the NAND circuits of the first control inverter, wherein a substantial L-size (transistor length) of the second control inverter may preferably be two times an L-size of the first control inverter.
When the number of inverters disposed is different, the substantial L-size of the transistors may be changed, and the switches can be switched substantially simultaneously without a delay. By this, the field through at the time of switching can be cancelled, and a voltage change due to charge noises can be controlled, such that a prolongation of the amplifier response can be suppressed.
In the chopper type comparator described above, two P-channel transistors disposed in parallel and two N-channel transistors disposed in series may preferably be disposed in the first control inverter, and four P-channel transistors disposed in parallel, and four N-channel transistors disposed in series may preferably be disposed in the second control inverter.
In the control driver circuit in this example, even when basic cells, which are often used in gate array ASICs, as the transistors, channel conductance xcex2N and xcex2P can be made generally equal to one another, and the switches can be switched substantially simultaneously without a delay. By this, the field through at the time of switching can be cancelled, and a voltage change due to charge noises can be controlled, such that an elongation of the amplifier response can be suppressed.
In the chopper type comparator described above, two P-channel transistors disposed in parallel and two N-channel transistors disposed in series are disposed in the first control inverter, and four P-channel transistors disposed in series, and four N-channel transistors disposed in series are disposed in the second control inverter.
In the control driver described above also, the switches can be switched substantially simultaneously without a delay. By this, the field through at the time of switching can be cancelled, and a voltage change due to charge noises can be controlled, such that an elongation of the amplifier response can be suppressed.